Invensas Corporation

New Approaches to Develop a Scalable 3D IC Assembly Method

Aug 11, 2016 | Charles G. Woychik Ph.D. Sangil Lee, Ph.D., Scott McGrath, Eric Tosaya and Sitaram Arkalgud Ph.D.

The challenge for 3D IC assembly is how to manage warpage and thin wafer handling in order to achieve a high assembly yield and to ensure that the final structure can pass the specified reliability requirements. Our test vehicles have micro-bumped die having pitches ranging from 60um down to 30um. The high density of pads and the large die size, make it extremely challenging to ensure that all of the micro-bump interconnects are attached to a thin Si-interposer. In addition, the low standoff between the die and interposer make it difficult to underfill. A likely approach is to first attach the die to the interposer and then the die/interposer sub-assembly to the substrate. In this scenario, the die/interposer sub-assembly is comparable to a monolithic silicon die that can be flip chip attached to the substrate.

In this paper, we will discuss various assembly options and the challenges posed by each. In this investigation, we will propose the best method to do 2.5D assembly in an OSAT(Outsourced Assembly and Test) facility....

BVA: Molded Cu Wire Contact Solution for Very High Density Package-on- Package (PoP) Applications

Jan 28, 2015 | Vern Solberg, Ilyas Mohammed

Stacking heterogeneous semiconductor die (memory and logic) within the same package outline can be considered for less complex applications but combining the memory and processor functions in a single package has compromised test efficiency and overall package assembly yield. Separation and packaging the semiconductor functions into sections, on the other hand, has proved to be more efficient and, even though two interposers are required, more economical. The separated logic and memory sections are configured with the same uniform outline for vertical stacking (package-on-package). The most common configuration places the logic section as the base with second tier memory section soldered to a mating contact pattern.

This paper addresses the primary technological challenges for reducing contact pitch and package-on-package interface technology....

Near Term Solutions For 3D Packaging Of High Performance DRAM

Sep 15, 2011 | Vern Solberg, Wael Zohni

The revolution in performance driven electronic systems continues to challenge the IC packaging industry. To enable the new generations of processors to reach their performance potential many manufacturers have developed interface formats to enable greater memory bandwidth. To ensure that the memory functions are able to support the increased signal speed, package developers are relying more and more on innovative 3D package assembly techniques and process refinement....