MacDermid Inc.

Innovative Electroplating Processes for IC Substrates - Via Fill, Through Hole Fill, and Embedded Trench Fill

Jun 21, 2021 | Saminda Dharmarathna , Sy Maddux , Chao Benjamin , Ivan Li , William Bowermana , Kesheng Feng , Jim Watkowski

In this era of electronics miniaturization, high yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate, the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has created unique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity, which measures how flat the top of the traces and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points, like vias and traces. Therefore, plating solutions that provide a uniform, planar profile without any special post treatment are quite desirable....

Via Fill and Through Hole Plating Process with Enhanced TH Microdistribution

Jul 17, 2019 | Maria Nikolova, Confesol Rodriguez, Kesheng Feng, Carmichael Gugliotti, William Bowerman, Jim Watkowski, Bob Wei

The increased demand for electronic devices in recent years has led to an extensive research in the field to meet the requirements of the industry. Electrolytic copper has been an important technology in the fabrication of PCBs and semiconductors. Aqueous sulfuric acid baths are explored for filling or building up with copper structures like blind micro vias (BMV), trenches, through holes (TH), and pillar bumps. As circuit miniaturization continues, developing a process that simultaneously fills vias and plates TH with various sizes and aspect ratios, while minimizing the surface copper thickness is critical. Filling BMV and plating TH at the same time, presents great difficulties for the PCB manufactures. The conventional copper plating processes that provide good via fill and leveling of the deposit tend to worsen the throwing power (TP) of the electroplating bath. TP is defined as the ratio of the deposit copper thickness in the center of the through hole to its thickness at the surface.</p> <p>In this paper an optimization of recently developed innovative, one step acid copper plating technology for filling vias with a minimal surface thickness and plating through holes is presented....

Advanced Cu Electroplating Process for Any Layer Via Fill Applications with Thin Surface Copper

Jun 26, 2019 | Saminda Dharmarathna, Christian Rietmann, William Bowerman, Kesheng Feng, Jim Watkowski

Copper-filled micro-vias are a key technology in high density interconnect (HDI) designs that have enabled increasing miniaturization and densification of printed circuit boards for the next generation of electronic products. Compared with standard plated through holes (PTHs) copper filled vias provide greater design flexibility, improved signal performance, and can potentially help reduce layer count, thus reducing cost. Considering these advantages, there are strong incentives to optimize the via filling process. This paper presents an innovative DC acid copper via fill formulation, for VCP (Vertical Continues Plating) applications which rapidly fills vias while minimizing surface plating....

High Throw DC Acid Copper Formulation for Vertical Continuous Electroplating Processes

Oct 31, 2018 | Saminda Dharmarathna, PhD, Ivan Li, PhD, Maddux Sy, Eileen Zeng, Bob Wei, William Bowerman, Kesheng Feng, PhD

The electronics industry has grown immensely over the last few decades owing to the rapid growth of consumer electronics in the modern world. New formulations are essential to fit the needs of manufacturing printed circuit boards and semiconductors. Copper electrolytes for high throwing power applications with high thermal reliability and high throughput are becoming extremely important for manufacturing high aspect ratio circuit boards.

Here we discuss innovative DC copper metallization formulations for hoist lines and VCP (Vertical Continues Plating) applications with high thermal reliability and throughput for high aspect ratio PCB manufacturing...

Semi-Additive Process for Low Loss Build-Up Material in High Frequency Signal Transmission Substrates

Apr 18, 2018 | Fei Peng, Naomi Ando, Roger Bernards, Bill Decesare

Higher functionality, higher performance and higher reliability with smaller real estate are the mantras of any electronic device and the future guarantees more of the same. In order to achieve the requirements of these devices, designs must incorporate fine line and via pitch while maintain good circuitry adhesion at a smooth plating-resin interface to improve signal integrity. The Semi-Additive Process (SAP) is a production-proven method used on low dielectric loss tangent (Df) build-up materials that enables the manufacture of ultra-fine circuitry. (...)

This paper will discuss a new SAP process for low loss build-up materials with low desmear roughness (Ra= 40-100 nm) and excellent adhesion (610-680 gf/cm) at various processing conditions. Along with the process flow, the current work will also present results and a discussion regarding characterization on the morphology and composition of resin and/or metal plating surfaces using scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX), surface roughness analysis, plating-resin adhesion evaluation from 90o peel tests...

Lean Six Sigma Approach to New Product Development

Aug 02, 2017 | Rita Mohanty

In this rapidly moving electronics market, fast to market with new products is what separates top performing companies from average companies. A survey conducted by Arthur D. Little revealed that "New-Product Development (NPD) productivity in atop performing company is five times what it is in the average company. The top performer gets five times as much new product output for the same investment." What do they know that the rest of us do not? One winning factor is the use of the Robert Cooper process. (...)

This paper will present a Lean Six Sigma approach to "right sizing" the Stage Gate process to be efficient, practical, and easy to manage. Various tools of Stage Gate, along with proven best practice, will be covered. In addition, a reduced Stage Gate model will be discussed for simple, low risk projects....

PCB Surface Finishes: A General Review

Jun 22, 2015 | Jun Nable, Ph.D., MacDermid Inc. Waterbury, CT

Surface finishing is an integral part of any PCB fabrication. It is generally applied to exposed Cu connectors and conductors on the board. Surface finishing has numerous important functions. It serves as a protective layer for the Cu connectors during storage. The surface finish helps minimize or reduce tarnish of the Cu substrate. Additionally, since it is the layer that comes into contact with other components during assembly, it ensures good solderability between the PCB and the component during assembly. Furthermore after assembly, the finish helps prolong the integrity of the solder joint during use.

A general review of common PCB surface finishes is presented. The advantages and disadvantages of each are discussed and compared. ...