Technical Articles From Intel Corporation

Package-on-Package (PoP) Warpage Characteristic and Requirement

Dec 16, 2021 | Wei Keat Loh, Ron Kulterman, Tim Purdie, Haley Fu, Masahiro Tsuriya

Package-on-Package (PoP) technology is widely used in mobile devices due to its simple design, lower cost and faster time to market. Warpage characteristic and requirement of PoP package becomes critical to ensure both the top and bottom package can be mounted with minimal yield lost. With this challenge in placed, iNEMI has been working relentlessly to fingerprint the current PoP package technology warpage characteristic and to establish some key learning for packaging technologies. The work also extended to understand the basic requirement needed for successful PoP stacking by analyzing the warpage data obtained and formulate a simple analytical equation to explain the true warpage requirement for PoP packaging....

Challenges of Manufacturing with Printed Circuit Board Cavities

Jan 06, 2021 | William O. Alger, Pedro J. Martinez, Weston C. Roth

Cavity technology in a Printed Circuit Board (PCB) has existed for many years. The methodology to create the cavity in the PCB has evolved over time as technologies have advanced and the manufacturing process varies by the individual PCB...

Voids in Solder Joints

Dec 12, 2019 | Raiyo Aspandiar

Presented at SMTA Boise Expo and Tech Forum, March 20, 2018...

Preparing for Increased Electrostatic Discharge Device Sensitivity

Oct 08, 2015 | Julian A. Montoya, Intel Corporation Hillsboro, Oregon

With the push for ever improving performance on semiconductor component I/O interfaces, semiconductor components are being driven into a realm which makes them more sensitive to electrostatic discharge, potentially increasing in sensitivity by 50% every 3-5 years. Today, the majority of modern day semiconductor components are being designed to meet 250Volts of charge device model sensitivity, and that could decrease to 125Volts in the next 3-5 years, and could again decrease to 50Volts-70Volts in the following 3-5 years. The entire electronics industry must prepare for this challenge....

Stereo Vision Based Automated Solder Ball Height Detection

Apr 16, 2015 | Jinjin Li, Lina J. Karam; School of Electrical, Computer, & Energy Engineering, Arizona State University, Bonnie L. Bennett, Jeff S. Pettinato;Intel Corporation.

Solder ball height inspection is essential to the detection of potential connectivity issues in semi-conductor units. Current ball height inspection tools such as laser profiling, fringe projection and confocal microscopy are expensive, require complicated setup and are slow, which makes them difficult to use in a real-time manufacturing setting. Therefore, a reliable, in-line ball height measurement method is needed for inspecting units undergoing assembly. (...)

In this paper, an automatic, stereo vision based, in-line ball height inspection method is presented. The proposed method includes an imaging setup together with a computer vision algorithm for reliable, in-line ball height measurement....

iNEMI HFR-Free PCB Materials Team Project: An Investigation to Identify Technology Limitations Involved in Transitioning to HFR-Free PCB Materials

May 16, 2013 | John Davignon, iNEMI Chair

In response to a growing concern within the Electronic Industry to the transition to Halogen-Free laminates (HFR-Free) within the Client Market space (Desktop and Notebook computers) iNEMI initiated a HFR-Free Leadership Workgroup to evaluate the readiness of the Industry to make this transition. The HFR-Free Leadership WG concluded that the electronic industry is ready for the transition and that the key electrical and thermo-mechanical properties of the new HFR-Free laminates can meet the required criteria. The HFR-Free Leadership WG verified that the laminate suppliers can meet the capacity demands for these new HFR-Free laminates and developed a "Test Suite Methodology" (TSM) that can facilitate the comparison and choice of the right laminate to replace brominated FR4 in the Client space... First published in the 2012 IPC APEX EXPO technical conference proceedings....

A Study of PCB Insertion Loss Variation in Manufacturing Using a New Low Cost Metrology

Jun 27, 2012 | Chu-tien Chia, Richard Kunze, David Boggs, Margaret Cromley

First published in the 2012 IPC APEX EXPO technical conference proceedings. Signal integrity analysis has shown that printed circuit board (PCB) insertion loss is a key factor affecting high speed channel performance. Determining and controlling PCB inser...

Implementation of a High-Quality Dolby* Digital Decoder Using MMX™ Technology

May 07, 1999 | James C. Abel, Michael A. Julier

Software decoding of Dolby Digital allows it to become a baseline capability on the PC, with greater flexibility than a hardware approach. Intel's MMX™ technology provides instructions that can significantly speed up the execution of the Dolby Digital decoder, freeing up the processor to perform other tasks such as video decoding and/or audio enhancement. Intel has worked closely with Dolby Laboratories to define an implementation of Dolby Digital based on MMX technology that has achieved Dolby's certification of quality....

MMX™ Microarchitecture of Pentium® Processors With MMX Technology and Pentium® II Microprocessors

May 07, 1999 | Michael Kagan, Simcha Gochman, Doron Orenstien, Derrick Lin

The MMX™ technology is an extension to the Intel Architecture (IA) aimed at boosting the performance of multimedia applications. This technology is the most significant IA extension since the introduction of the Intel386™ microprocessor. The challenge in implementing this technology came from retrofitting the new functionality into existing Pentium® and Pentium® Pro processor designs....

MMX™ Technology Architecture Overview

May 07, 1999 | Millind Mittal, Alex Peleg, Uri Weiser

Media (video, audio, graphics, communication) applications present a unique opportunity for performance boost via use of Single Instruction Multiple Data (SIMD) techniques. While several of the computeintensive parts of media applications benefit from SIMD techniques, a significant portion of the code still is best suited for general purpose instruction set architectures. MMX™ technology extends the Intel Architecture (IA), the industry's leading general purpose processor architecture, to provide the benefits of SIMD for media applications....

A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS Logic Process

May 07, 1999 | Intel Corp.

A novel programmable element has been developed and evaluated for state of the art CMOS processes. This element is based on agglomeration of tVarious aspects of these programmable devices including characterization and optimization of physical and electrical aspects of the element, programming yield, and reliability have been studied. Development ofhe Ti-silicide layer on top of poly fuses. ...

Redundancy and High-Volume Manufacturing Methods

May 07, 1999 | Christopher W. Hampson, MD6 Cache Product Engineering, Hillsboro, OR, Intel Corp.

This paper will describe practical aspects of a redundancy implementation on a high-volume cache memory product. Topics covered include various aspects of redundancy from a design and product engineering perspective; and present test development methods for future product implementations....

Redundancy Yield Model for SRAMS

May 07, 1999 | Nermine H. Ramadan, STTD Integration/Yield, Hillsboro, OR, Intel Corp.

This paper describes a model developed to calculate number of redundant good die per wafer. A block redundancy scheme is used here, where the entire defective memory subarray is replaced by a redundant element. A formula is derived to calculate the amount of improvement expected after redundancy. This improvement is given in terms of the ratio of the overall good die per wafer to the original good die per wafer after considering some key factors....

Intel StrataFlash™ Memory Development and Implementation

May 07, 1999 | Al Fazio, Mark Bauer

This paper will review the device physics governing the operation of the industry standard ETOX™ flash memory cell and show how it is ideally suited for multiple bit per cell storage, through its storage of electrons on an electrically isolated floating gate and through its direct access to the memory cell....

Intel StrataFlash™ Memory Technology Overview

May 07, 1999 | Greg Atwood, Al Fazio, Duane Mills, Bill Reaves

The Intel StrataFlashTM memory technology represents a cost breakthrough for flash memory devices by enabling the storage of two bits of data in a single flash memory transistor. This paper will discuss the evolution of the two bit/cell technology from conception to production....

Illinois-Intel Multithreading Library: Multithreading Support for Intel Architecture Based Multiprocessor Systems

May 07, 1999 | Milind Girkar, Mohammad R. Haghighat, Paul Grey, Hideki Saito, Nicholas J. Stavrakos, Constantine D. Polychronopoulos

Powerful desktop multiprocessor systems based on the Intel Architecture (iA) offer a formidable alternative to traditional scientific/engineering workstations for commercial application developers at an attractive costperformance ratio. However, the lack of adequate compiler and runtime library support for multithreading and parallel processing on Windows NT* makes it difficult or impossible to fully exploit the performance advantage of these multiprocessor systems. In this paper we describe the design, development, and initial performance results of the Illinois-Intel Multithreading Library (IML), which aims at providing an efficient and powerful (in terms of types of parallelism it supports) API for multithreaded application developers....

Scalable Platform Services on the Intel TFLOPS Supercomputer

May 07, 1999 | Bradley Mitchell; Server Software Technology

This paper describes Scalable Platform Services (SPS)- a collection of software providing the manageability solution for Intel's latest parallel processing supercomputer. ...

Achieving Large Scale Parallelism Through Operating System Resource Management on the Intel TFLOPS Supercomputer

May 07, 1999 | Sharad Garg, Robert Godley, Richard Griffiths, Andrew Pfiffer, Terry Prickett, David Robboy, Stan Smith, T. Mack Stallcup, Stephan Zeisset.

From the point of view of an operating system, a computer is managed and optimized in terms of the application programming model and the management of system resources. For the TFLOPS system, the problem is to manage and optimize large scale parallelism. This paper looks at the management in terms of three key topics: memory management, communication, and input/output....

The Performance of the Intel TFLOPS Supercomputer

May 07, 1999 | Greg Henry, Pat Fay, Ben Cole, Timothy G. Mattson.

The purpose of building a supercomputer is to provide superior performance on real applications. In this paper, we describe the performance of the Intel TFLOPS Supercomputer starting at the lowest level with a detailed investigation of the Pentium® Pro processor and the supporting memory subsystem....

An Overview of the Intel TFLOPS Supercomputer

May 07, 1999 | Timothy G. Mattson, Greg Henry

In this paper, we give an overview of the ASCI Option Red Supercomputer. The motivation for building this supercomputer is presented and the hardware and software views of the machine are described in detail. We also briefly discuss what it is like.....

Computer Vision Face Tracking For Use in a Perceptual User Interface

May 07, 1999 | Gary R. Bradski; Microcomputer Research Lab

As a first step towards a perceptual user interface, a computer vision color tracking algorithm is developed and applied towards tracking human faces. Computer vision algorithms that are intended to form part of a perceptual user interface must be fast and efficient. They must be able to track in real time yet not absorb a major share of computational resources: other tasks must be able to run while the visual interface is being used. The new algorithm developed here is based on a robust nonparametric technique for climbing density gradients to find the mode (peak) of probability distributions called the mean shift algorithm....

An Overview of Advanced Failure Analysis Techniques for Pentium® and Pentium® Pro Microprocessors

May 07, 1999 | Yeoh Eng Hong, Lim Seong Leong, Wong Yik Choong, Lock Choon Hou, Mahmud Adnan; Intel Penang Microprocessor Failure Analysis Department, Malaysia

Failure analysis (FA) is one of the key competencies in Intel. It enables very rapid achievement of world class manufacturing standards, resulting in excellent microprocessor time-to-market performance. This paper discusses the evolution of FA techniques from one generation of microprocessors to another....

EUV Lithography -The Successor to Optical Lithography?

May 07, 1999 | John E. Bjorkholm

This paper discusses the basic concepts and current state of development of EUV lithography (EUVL), a relatively new form of lithography that uses extreme ultraviolet (EUV) radiation with a wavelength in the range of 10 to 14 nanometer (nm) to carry out projection imaging. Currently, and for the last several decades, optical projection lithography has been the lithographic technique used in the high-volume manufacture of integrated circuits. It is widely anticipated that improvements in this technology will allow it to remain the semiconductor industry's workhorse through the 100 nm generation of devices. However, some time around the year 2005, so-called Next-Generation Lithographies will be required. ...

MOS Scaling: Transistor Challenges for the 21st Century

May 07, 1999 | Scott Thompson, Paul Packan, Mark Bohr

To enable transistor scaling into the 21st century, new solutions such as high dielectric constaConventional scaling of gate oxide thickness, source/drain extension (SDE), junction depths, and gate lengths have enabled MOS gate dimensions to be reduced from 10mm in the 1970’s to a present day size of 0.1mm. To enable transistor scaling into the 21st century, new solutions such as high dielectric constant materials for gate insulation and shallow, ultra low resistivity junctions need to be developed. In this paper, for the first time, key scaling limits are quantified for MOS transistorsnt materials for gate insulation and shallow, ultra low resistivity junctions need to be developed....

The Quality and Reliability of Intel's Quarter Micron Process

May 07, 1999 | Krishna Seshan, Timothy J. Maloney, Kenneth J. Wu

This paper describes how the quality and reliability of Intel's products are designed, measured, modeled, and maintained. Four main reliability topics: ESD protection, electromigration, gate oxide wearout, and the modeling and management of mechanical stresses are discussed. Based on an analysis of the reliability implications of device scaling, we show how these four topics are of prime importance to component reliability......

Manufacturing Operations System Design and Analysis

May 06, 1999 | C. Hilton, Manufacturing Strategic Support, Technology and Manufacturing Engineering, Intel Corp.

This paper describes manufacturing operations design and analysis at Intel. The complexities and forces of both the market and the manufacturing process combine to make the development of improved semiconductor fabrication manufacturing strategies (like lot dispatching, micro and macro scheduling policies, labor utilization, layout, etc.) particularly important......

The Evolution of Intel's Copy EXACTLY! Technology Transfer Method

May 06, 1999 | Chris J. McDonald , Intel SEMATECH

Semiconductor manufacturing is characterized by very complex process flows made up of individual process steps, many of which are built to very close tolerances. Furthermore, there are complex interactions in these process flows, whereby each process step can affect many other steps, and each final device parameter might be determined by the results from many inputs......

21st Century Semiconductor Manufacturing Capabilities

May 06, 1999 | Eugene S. Meieran, Intel Corp.

Semiconductor device manufacturers face many difficult challenges as we enter the 21st century. Some are direct consequences of adherence to Gordon Moore's Law, which states that device complexity doubles about every 18 months. Feature size reduction, increased wafer diameter, increased chip size, ultra-clean processing, and defect reduction among others are manifestations that have a direct bearing on the cost and quality of products, factory flexibility in responding to changing technology or business conditions, and on the timelines of product delivery to the ultimate customer....

Defect-Based Test: A Key Enabler for Successful Migration to structural test

May 06, 1999 | Sanjay Sengupta, Sandip Kundu, Sreejit Chakravart, Praveen Parvathal, Rajesh Galivanche, George Kosonocky, Mike Rodgers, TM Mak; MPG Test Technology, Intel Corp.

ntelís traditional microprocessor test methodology, based on manually generated functional tests that are applied at speed using functional testers, is facing serious challenges due to the rising cost of manual test generation and the increasing cost of high-speed testers. If current trends continue, the cost of testing a device could exceed the cost of manufacturing it. We therefore need to rely more on automatic test pattern generation (ATPG) and low-cost structural testers....

Challenges of CAD Development for Datapath Design

May 06, 1999 | Tim Chan, Amit Chowdhary, Bharat Krishna, Artour Levin, Gary Meeker, Naresh Sehga

In many high-performance VLSI designs, including all recent Intel microprocessors, datapath is implemented in a bit-sliced structure to simultaneously manipulate multiple bits of data. The circuit and layout of such structures are largely kept the same for each bit slice to achieve maximal performance, higher designer productivity, and better layout density. There are very few tools available to automate the design of a general datapath structure, most of which is done manually......

Nike's Software Architecture and Infrastructure: Enabling Integrated Solutions for Gigahertz Designs

May 06, 1999 | Nike Development, DT, Intel Corp.

This paper describes how Nike’s innovative architecture addresses the expanding requirements of Intel’s next-generation processor designs while enabling a design environment that is more productive than one built with the previous tool generation....

Intel Packaging Databook

Apr 15, 1999 | Intel Corporation

Intel's Packaging Databook is intended to serve as a data reference for engineering design, as well as a guide to Intel package selection and availability. IC assembly, performance characteristics, physical constants, detailed discussions of SMT, etc....