Electronics Manufacturing Technical Articles

Control of the Underfill of Surface Mount Assemblies by Non-Destructive Techniques

Apr 28, 2016 | Julien Perraud, Arnaud Grivon.

Underfilling is a long-standing process issued from the micro-electronics that can enhance the robustness and the reliability of first or second-level interconnects for a variety of electronic applications. Its usage is currently spreading across the industry fueled by the decreasing reliability margins induced by the miniaturization and interconnect pitch reduction. (...)

This paper will address the control of surface mount under filled assemblies, focusing on applicable inspection techniques and possible options to overcome their limitations....

Publisher: THALES

3D Assembly Process a Look at Today and Tomorrow

Apr 21, 2016 | David Geiger, Georgie Thein; AEG, Flextronics International Inc.

The world of electronics continues to increase functional densities on products. One of the ways to increase density of a product is to utilize more of the 3 dimensional spaces available. Traditional printed circuit boards utilize the x/y plane and many miniaturization techniques apply to the x/y space savings, such as smaller components, finer pitches, and closer component to component distances.

This paper will explore the evolution of 3D assembly techniques, starting from flexible circuit technology, cavity assembly, embedded technology, 3 dimensional surface mount assembly, etc....

Publisher: Flex (Flextronics International)

Causes and Costs of No Fault Found Events

Apr 14, 2016 | Louis Y. Ungar

A system level test, usually built-in test (BIT), determines that one or more subsystems are faulty. These subsystems sent to the depot or factory repair facility, called units under test (UUTs) often pass that test, an event we call No-Fault-Found (NFF). With more-and more electronics monitored by BIT, it is more likely that an intermittent glitch will trigger a call for a maintenance action resulting in NFF. NFFs are often confused with false alarm (FA), cannot duplicate (CNDs)or retest OK (RTOK) events. NFFs at the depot are caused by FAs, CNDs, RTOKs as well as a number of other complications. Attempting to repair NFF scan waste precious resources, compromise confidence in the product, create customer dissatisfaction, and the repair quality remains a mystery. The problem is compounded by previous work showing that most failure indications calling for repair action at the system level are invalid. NFFs can be caused by real failures or may be a result of system level false alarms. Understanding the cause of the problem may help us distinguish between units under test (UUTs) that we can repair and those that we cannot. In calculating the true cost of repair we must account for wasted effort in attempting to repair unrepairable UUTs.

This paper will shed some light on this trade-off. Finally, we will explore approaches for dealing with the NFF issue in a cost effective manner....

Publisher: A.T.E. Solutions, Inc.

Streamlining PCB Assembly and Test NPI with Shared Component Libraries

Apr 08, 2016 | Julian Coates

PCB assembly designs become more complex year-on-year, yet early-stage form/fit compliance verification of all designed-in components to the intended manufacturing processes remains a challenge. So long as librarians at the design and manufacturing levels continue to maintain their own local standards for component representation, there is no common representation in the design-to-manufacturing phase of the product lifecycle that can provide the basis for transfer of manufacturing process rules to the design level. A comprehensive methodology must be implemented for all component types, not just the minority which happen to conform to formal packaging standards, to successfully left-shift assembly and test DFM analysis to the design level and thus compress NPI cycle times.(...)

This paper will demonstrate the technological components of the working solution: the logic for deriving repeatable and standardized package and pin classifications from a common source of component physical-model content, the method for associating DFA and DFT rules to those classifications, and the transfer of those rules to separate DFM and NPI analysis tools elsewhere in the design-through-manufacturing chain resulting in a consistent DFM process across multiple design and manufacturing organizations....

Publisher: Mentor Graphics

EMI-Caused EOS Sources in Automated Equipment

Mar 31, 2016 | Vladimir Kraz

Electrical overstress causes damage to sensitive components, including latent damage. A significant source of EOS is high-frequency noise in automated manufacturing equipment. This paper analyses sources of such noise, how it affects components and how to mitigate this problem....

Publisher: OnFILTER, Inc.

Cable and Harness Manufacturing: Five Qs to ask when selecting a Cable and Harness Tester ...

Mar 25, 2016 | Margaret Bishop (CAMI Research)

Ready to purchase a new tester? Interested in improving productivity & quality? Ask these technical questions of your potential supplier....

Publisher: CAMI Research Inc.

High Frequency DK and DF Test Methods Comparison High Density Packaging User Group (HDP) Project

Mar 24, 2016 | Karl Sauter; Oracle Corporation, Joe Smetana; Alcatel-Lucent

Today's Electronic Industry is changing at a high pace. The root causes are manifold. So world population is growing up to eight billions and gives new challenges in terms of urbanization, mobility and connectivity. Consequently, there will raise up a lot of new business models for the electronic industry. Connectivity will take a large influence on our lives. Concepts like Industry 4.0, internet of things, M2M communication, smart homes or communication in or to cars are growing up. All these applications are based on the same demanding requirement – a high amount of data and increased data transfer rate. These arguments bring up large challenges to the Printed Circuit Board (PCB) design and manufacturing.

This paper investigates the impact of different PCB manufacturing technologies and their relation to their high frequency behavior. In the course of the paper a brief overview of PCB manufacturing capabilities is be presented. Moreover, signal losses in terms of frequency, design, manufacturing processes, and substrate materials are investigated. The aim of this paper is, to develop a concept to use materials in combination with optimized PCB manufacturing processes, which allows a significant reduction of losses and increased signal quality....

Publisher: Alcatel-Lucent

Enabling High-Speed Printing Using Low-Cost Materials: Process Stability is Paramount

Mar 17, 2016 | Michael L. Cieslinski, Brent A. Fischthal

The rapid growth of electronic devices across the globe is driving manufacturers to enhance high-speed mass production techniques in the PCB assembly arena. As manufacturers drive to reduce costs while maximizing production by expanding facilities, updating automation equipment, or implementing lean six sigma techniques, the potential to build scrap product or rework printed circuit boards increases dramatically.

Manufacturers have two general paths to reduce the costs of high-speed printed circuit board assembly production. The first path is to reduce cost by focusing on high quality printing and mounting. The other, increasingly popular option is to utilize low-cost materials. In either case, the baseline must provide a consistent high-speed solder paste printing method, which considers the fill, snap-off, and cleaning processes.

Building on our expertise and testing, this paper will highlight the two trains of thought with specific focus on how low-cost materials affect print performance. It will also explore technologies, which can help provide stable, high-speed screen printing....

Publisher: Panasonic Factory Solutions Company of America (PFSA)

Acceptance Testing Of Low-Ag Reflow Solder Alloys

Mar 10, 2016 | Kris Troxel, Aileen Allen, Elizabeth Elias Benedetto, Rahul Joshi

Since the implementation of the European Union RoHS directive in 2006, the electronics industry has seen an expansion of available low-silver lead (Pb)-free1 alloys for wave soldering, miniwave rework, BGA and CSP solder balls, and, more recently, solder pastes for mass reflow. The risks associated with the higher processing temperatures of these low-silver (Ag between 0-3 wt%) solder alloys, such as potential laminate or component damage, increased copper dissolution, and reduced thermal process windows may present manufacturing challenges and possible field reliability risks for original equipment manufacturers (OEMs). In order to take advantage of potential cost reduction opportunities afforded by these new alloys, while mitigating manufacturing and reliability risks, the company has defined test protocols [1-4] that can be used for assessing new Sn-Ag-Cu(SAC), Sn-Ag, and Sn-Cu alloys for general use in electronics.

This paper describes initial test results for low-silver alloys using these solder paste alloy assessment protocols for BGAs and leaded components, and the impact of the alloys on printed circuit assembly process windows....

Publisher: HP Inc.

Nanocopper Based Paste for Solid Copper Via Fill

Mar 03, 2016 | David Ciufo, Sujatha Ramanujan, Janet Heyen, Michael Carmody; Intrinsiq Materials, Sunny Patel; Candor Industries.

This paper discusses a nano copper based paste for use in via filling. The company manufactures nano copper and disperses the coated nano copper into a paste in combination with micron copper. The resultant paste is injected or fills a via. The via is subsequently sintered by means of photonic sintering, or by heat in a reducing environment. The process will be accomplished in under an hour and results in filled solid copper vias....

Publisher: Intrinsiq Materials Inc.

ph Neutral Cleaning Agents - Market Expectation & Field Performance

Feb 25, 2016 | Umut Tosun, Jigar Patel, Kalyan Nukula, Fernando Gazcon, ZESTRON America

With regard to precision cleaning applications within electronics manufacturing, pH neutral product development was a major breakthrough in recent years. The impetus for this development resulted from changes with regard to solder paste formulations and resulting assembly processes.</p><p>The greater use of lead-free solder paste and the required higher reflow profiles have resulted in even more difficult to remove burnt-in flux residues. Coupled with increases in component density, larger component packages, higher lead counts, finer lead spacing, and lower standoff distances, effective cleaning is greatly challenged. The aqueous alkaline based cleaning agents can effectively remove these flux residues, however, the process often requires an increase in wash temperature and exposure time, chemical concentration, and mechanical energy. Although an efficient and effective cleaning process can be developed, oftentimes, the required operating parameters present a new set of challenges with regard to material compatibility.</p><p>Since their introduction, the newly developed pH neutral formulations have proven to be capable not only of removing these difficult post reflow residues from complex board geometries, but do so without affecting material compatibility of sensitive components. Additionally, they perform at low concentration levels. This study reviews the performance of pH neutral cleaning agents as compared to alkaline cleaning agent alternatives and includes field data demonstrating their effectiveness with regard to material compatibility and cleaning performance....

Publisher: ZESTRON Americas

Sample Preparation For Mitigating Tin Whiskers In Alternative Lead-Free Alloys

Feb 18, 2016 | Mehran Maalekian, Karl Seelig, Timothy O'Neill

As lead-free alloys shift into high reliability electronics, the issue of tin whisker growth remains a primary concern among those in the industry. Current research shows that there is no perfect alloy for all cases of electronic usage. Industry leaders and researchers continue to study and search for a lead free alloy that is able to withstand harsh environments while maintaining high reliability....

Publisher: AIM Solder

Effective Methods to Get Volatile Compounds Out of Reflow Process

Feb 11, 2016 | Gerjan Diepstraten

Although reflow ovens may not have been dramatically changed during the last decade the reflow process changes step by step. With the introduction of lead-free soldering not only operation temperatures increased, but also the chemistry of the solder paste was modified to meet the higher thermal requirements. Miniaturization is a second factor that impacts the reflow process. The density on the assembly is increasing where solder paste deposit volumes decreases due to smaller pad and component dimensions. Pick and place machines can handle more components and to meet this high through put some SMD lines are equipped with dual lane conveyors, doubling solder paste consumption. With the introduction of pin in paste to solder through hole components contamination of the oven increased due to dripping of the paste....

Publisher: Vitronics Soltec

Make the Right Design Choices in Load Switching and Simulation in a High Current and Mechatronic Functional Test

Feb 04, 2016 | Derek Ong, Lok Teng Kee, Chuah Rhun Chia

In a typical mechatronic manufacturing functional test setup, actual load simulations are usually done by connecting the DUT outputs to power or ground in order to establish either a high or low side driver. Each output is connected with different load and the test will either be sequential or concurrent. At lower power levels, these can usually be managed with general purpose switches. However, when it comes to higher power levels of currents more than 5 amps, such switching and loading might pose a greater challenge. Furthermore, critically in the manufacturing line, the tradeoff between cost and test time would have a great influence on the test strategy.

This paper will present some key points to design a cost effective high power switching and load management solution....

Publisher: Keysight Technologies

Dispelling the Black Magic of Solder Paste

Jan 21, 2016 | Tony Lentz

Solder paste has long been viewed as "black magic". This "black magic" can easily be dispelled through a solder paste evaluation. Unfortunately, solder paste evaluation can be a challenge for electronic assemblers. Interrupting the production schedule to perform an evaluation is usually the first hurdle. Choosing the solder paste properties to test is simple, but testing for these properties can be difficult. Special equipment or materials may be required depending upon the tests that are chosen. Once the testing is complete, how does one make the decision to choose a solder paste? Is the decision based on gut feel or hard data?

This paper presents a process for evaluating solder pastes using a variety of methods. These methods are quick to run and are challenging, revealing the strengths and weaknesses of solder pastes. Methods detailed in this paper include: print volume, stencil life, response to pause, open time, tack force over time, wetting, solder balling, graping, voiding, accelerated aging, and others....

Publisher: FCT ASSEMBLY, INC.

A Low Cost Manufacturing Solution - Low Temperature Super-Fast Cure and Flow Reworkable Underfill

Jan 12, 2016 | Dr. Mary Liu and Dr. Wusheng Yin

In order to meet the increasing demand of device miniaturization, high speed, more memory, more function, low cost, and more flexibility in device design and manufacturing chain, underfilling has increasingly become an essential process for the good reliability of electronic devices. Filled capillary underfill has been selected for used in package-level where there is large thermal stress caused by CTE mismatch issue, but the underfill is usually not reworkable. Unfilled capillary underfill has been used for board-level application such as BGA/CSP, POP, WL-CSP where there is need for mechanical shock resistance, the underfill is usually reworkable....

Publisher: YINCAE Advanced Materials, LLC.

A Room Temperature Stable and Jetable Solder Joint Encapsulant Adhesive - Capillary Underfill Replacement

Jan 12, 2016 | Dr. Mary Liu and Dr. Wusheng Yin

With the increasing demand of device miniaturization, high speed, more memory, more function, low cost, and more flexibility in device design and manufacturing chain, YINCAE has published a white paper on a first individual solder joint encapsulant which can eliminate underfilling process with at least five times solder joint increase and provide more flexibility for fine pitch and high density application. In order to meet the demand of manufacturing of high speed and low cost, YINCAE has invented a room temperature stable and jettable solder joint encapsulant adhesive – SMT 266. The invention of SMT 266 has allowed our customers to have more flexibility in their high-speed production line such as worry free on the work life of adhesive and workable jetting process....

Publisher: YINCAE Advanced Materials, LLC.

A Low Temperature Solder Joint Encapsulant for Sn/Bi Applications

Jan 12, 2016 | Dr. Mary Liu and Dr. Wusheng Yin

The electronic industry is currently very interested in low temperature soldering processes such as using Sn/Bi alloy to improve process yield, eliminate the head-in-pillow effect, and enhance rework yield. However, Sn/Bi alloy is not strong enough to replace lead-free (SAC) and eutectic Sn/Pb alloys in most applications. In order to improve the strength of Sn/Bi solder joints, enhance mechanical performance, and improve reliability properties such as thermal cycling performance of soldered electronic devices, YINCAE has developed a low temperature solder joint encapsulant for Sn/Bi soldering applications. This low temperature solder joint encapsulant can be dipped, dispensed, or printed. After reflow with Sn/Bi solder paste or alloy, solder joint encapsulant encapsulates the solder joint. As a result, the strength of solder joints is enhanced by several times, and thermal cycling performance is significantly improved. All details will be discussed in this paper....

Publisher: YINCAE Advanced Materials, LLC.

Solderable Anisotropic Conductive Adhesives for 3D Package Applications

Jan 12, 2016 | Dr. Mary Liu and Dr. Wusheng Yin

3D packaging has recently become very attractive because it can provide more flexibility in device design and supply chain, reduce the gap between silicon die and organic substrate, help miniaturize devices and meet the demand of high speed, provide more memory, more function and low cost. With the advancement of 3D packaging, the bump height is now down from 80μ to 10μ. When the bump diameter is 20-40μ and height 10μ, the process and reliability are obvious issues. It is well known that underfill can enhance the reliability for regular flip chip, however underfill won’t help assembly process. In order to resolve some difficulties that 3D packaging faces, YINCAE Advanced Materials, LLC has developed solderable anisotropic conductive adhesives for 3D package applications. In this paper we will discuss the assembly process and reliability in detail....

Publisher: YINCAE Advanced Materials, LLC.

An Innovative Reliability Solution to Interconnect of Flexible/Rigid Substrates

Jan 12, 2016 | Dr. Mary Liu and Dr. Wusheng Yin

With the pitch size of interconnect getting finer and finer, the bonding strength between flexible and rigid (e.g. PCB, ceramic) substrates becomes a serious issue because it is not strong enough to meet the customer’s requirement. Capillary underfill has been used to enhance the bonding strength between flexible and rigid substrates, but the enhancement is very limited, particularly for high temperature application. The bonding strength of underfilled flexible/rigid interconnect is dramatically decreased after being used at 180◦C, and the interconnects are weakened by the internal stress caused by the expansion of underfill at high temperatures. In order to resolve reliability issues of the interconnect between flexible/rigid substrates, solder joint encapsulant was implemented into the thermal compression bonding process, which was used to manufacture the interconnect between flexible/rigid substrates. Compared to the traditional process, the strength of the interconnect was doubled and the reliability was significantly improved in high temperature application....

Publisher: YINCAE Advanced Materials, LLC.

Solder Joint Encapsulant Adhesive - LGA High Reliability And Low Cost Assembly Solution

Jan 12, 2016 | Dr. Mary Liu and Dr. Wusheng Yin

More and more Land Grid Array (LGA) components are being used in electronic devices such as smartphones, tablets and computers. In order to enhance LGA mechanical strength and reliability, capillary flow underfill is used to improve reliability. However, due to the small gap, it is difficult for capillary underfill to flow into the LGA at SMT level. Due to cost considerations, there are usually no pre-heating underfill or cleaning flux residue processes at the SMT assembly line. YINCAE solder joint encapsulant SMT256 has been successfully used with solder paste for LGA assembly. Solder joint encapsulant is used in in-line LGA soldering process with enhanced reliability. It eliminates the underfilling process and provides excellent reworkability. The shear st rength of solder joint is stronger than that of underfilled components. The thermal cycling performance using solder joint encapsulant is much better than that using underfill. Bottom IC of POP has been studied for further understanding of LGA assembly process parameters. All details such as assembly process, drop test and thermal cycling test will be discussed in this paper....

Publisher: YINCAE Advanced Materials, LLC.

The Future of Solder Joint Encapsulant

Jan 08, 2016 | Dr. Mary Liu and Dr. Wusheng Yin

Solder joint encapsulant adhesives have been successfully used to enhance the strength of solder joints and improve thermal cycling as well as drop performance in finished products. The use of solder joint encapsulant adhesives can eliminate the need for underfill materials and the underfill process altogether, thus simplifying rework, which results in a lower cost of ownership.

Solder joint encapsulant adhesives include: low temperature and high temperature solder joint encapsulant adhesives, and their derivatives. Each solder joint encapsulant adhesive has: unfilled and filled solder joint encapsulant adhesives, and solder joint encapsulant paste. Each solder joint encapsulant product has been designed for different applications. In this paper, we are going to discuss the details and future of solder joint encapsulant adhesives. ...

Publisher: YINCAE Advanced Materials, LLC.

Effect on Microwave Plasma Surface Treatment for Improved Adhesion Strenght of Direct Copper Plating on Polytetrafluoroethylene (PTFE)

Jan 07, 2016 | Akira Takeuchi, Takahiro Kurahashi, Kyosuke Takeda

The purpose of this study is to investigate the effect of plasma surface modification to improve adhesion strength between polytetrafluoroethylene (PTFE) and electroless copper plating. PTFE is widely used in many industries because of its unique electrical, thermal, and mechanical characteristics. However, because of its low surface energy, it is difficult to acquire enough adhesion strength between PTFE and other substances without surface modification. Plasma is well known as one of the surface modification techniques that improve adhesion strength....

Publisher: Nissin Corporation

Study on Solder Joint Reliability of Fine Pitch CSP

Dec 31, 2015 | Yong Hill Liang, Hank Mao, YongGang Yan, Jindong (King) Lee; AEG, Flextronics International.

Today's consumer electronic product are characterized by miniatuization, portability and light weight with high performance, especially for 3G mobile products. In the future more fine pitch CSPs (0.4mm) component will be required. However, the product reliability has been a big challenge with the fine pitch CSP. Firstly, the fine pitch CSPs are with smaller solder balls of 0.25mm diameter or even smaller. The small solder ball and pad size do weaken the solder connection and the adhesion of the pad and substrate, thus the pad will peel off easily from the PCB substrate. In addition, miniature solder joint reduce the strength during mechanical vibration, thermal shock, fatigue failure, etc. Secondly, applying sufficient solder paste evenly on the small pad of the CSP is difficult because stencil opening is only 0.25mm or less. This issue can be solved using the high end type of stencil such as Electroforming which will increase the cost....

Publisher: Flex (Flextronics International)

PCB Fabrication Processes and Their Effects on Fine Copper Barrel Cracks

Dec 23, 2015 | Edward Arthur, Charles Busa, Melissa Durfee, Chad Gibson, Wade Goldman P.E.; Raytheon Company, Space and Airborne Systems, The Charles Stark Draper Laboratory, Inc., Raytheon Company, Integrated Defense Systems.

The onset of copper barrel cracks is typically induced by the presence of manufacturing defects. In the absence of discernible manufacturing defects, the causes of copper barrel cracks in printed circuit board (PCB) plated through holes is not well understood. Accordingly, there is a need to determine what affects the onset of barrel cracks and then control those causes to mitigate their initiation.

The objective of this research is to conduct a design of experiment (DOE) to determine if there is a relationship between PCB fabrication processes and the prevalence of fine barrel cracks. The test vehicle used will be a 16-layer epoxy-based PCB that has two different sized plated through holes as well as buried vias....

Publisher: Raytheon

Good Product Quality Comes From Good Design for Test Strategies

Dec 17, 2015 | Adrian Cheong

Product quality can be improved through proper application of design for test (DFT) strategies. With today's shrinking product sizes and increasing functionality, it is difficult to get good test coverage of loaded printed circuit boards due to the loss of test access. Advances in test techniques, such as boundary scan, help to recover this loss of test coverage. However, many of these test techniques need to be designed into the product to be effective.

This paper will discuss how to maximize the benefits of boundary scan test, including specific examples of how designers should select the right component, connect multiple boundary scan components in chains, add test access to the boundary scan TAP ports, etc. A discussion of DFT guidelines for PCB layout designers is also included. Finally, this paper will include a description of some advanced test methods used in in-circuit tests, such as vectorless test and special probing methods, which are implemented to improve test coverage on printed circuit boards with limited test access....

Publisher: Agilent Technologies, Inc.

Looking Forward - Manufacturing Execution Systems for SME’s

Dec 14, 2015 | Pete Doyon, VP Product Management, Schleuniger, Inc.

A Manufacturing Execution System (MES) is a software program that manages and monitors production work in a factory. The MES controls and monitors all manufacturing data in real time, so there is no guesswork as to the status of any given job, machine, operator, etc. The focus is on short-interval scheduling (shift or day) with an emphasis on optimizing the distribution of work orders. Larger manufacturers have employed MES’s for years but many small to medium sized enterprises (SME’s) have yet to adopt such systems. The benefits of using an MES are many. Looking forward, I predict that even the smallest manufacturing companies will employ MES systems in the future....

Publisher: Schleuniger, Inc.

Packaging Technology and Design Challenge for Fine Pitch Micro-Bump Cu-Pillar and BOT (Direct Bond on Substrate-Trace) Using TCNCP

Dec 02, 2015 | Myung-June Lee -Altera Corporation, SungSoon Park, DongSu Ryu, MinJae Lee - Amkor Technology, Hank Saiki, Seiji Mori, Makoto Nagai - NTK Technologies.

(Thermal Compression with Non-Conductive Paste Underfill) Method.

The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.

Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).

This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology....

Publisher: Altera Corporation

HCFC-225 Phaseout - What Now?

Dec 01, 2015 | Ed Kanegsberg

On January 1, 2015, nine months from APEX 2014, the production and use restrictions on HCFC-225 will be in effect throughout the United States. This phase out is encompassing in scope. This phase out will have significant technical, performance, and economic implications for the electronics industry. The regulatory situation remains fluid. A number of alternative solvents have been or are in the process of being developed. We discuss the options for assemblers and component manufacturers....

Publisher: BFK Solutions LLC

Study of Various PCBA Surface Finishes

Nov 25, 2015 | Georgie Thein, David Geiger, and Murad Kurwa.

In this study various printed circuit board surface finishes were evaluated, including: organic solderability preservative (OSP), plasma finish (PF), immersion silver (IAg), electroless nickel / immersion silver (ENIS), electroless nickel / immersion gold hi-phosphorus (ENIG Hi-P), and electroless nickel / electroless palladium / immersion gold (ENEPIG). To verify the performance of PF as a post-treatment option, it was added to IAg, ENIG Hi-P, and ENEPIG to compare with non-treated. A total of nine groups of PCB were evaluated. Each group contains 30 boards, with the exception on ENIS where only 8 boards were available....

Publisher: Flex (Flextronics International)

HALT Testing of Backward Soldered BGAs on a Military Product

Nov 19, 2015 | B. Gumpert, B. Fox, L. Woody

The move to lead free (Pb-free) electronics by the commercial industry has resulted in an increasing number of ball grid array components (BGAs) which are only available with Pb-free solder balls. The reliability of these devices is not well established when assembled using a standard tin-lead (SnPb) solder paste and reflow profile, known as a backward compatible process. Previous studies in processing mixed alloy solder joints have demonstrated the importance of using a reflow temperature high enough to achieve complete mixing of the SnPb solder paste with the Pb-free solder ball. Research has indicated that complete mixing can occur below the melting point of the Pb-free alloy and is dependent on a number of factors including solder ball composition, solder ball to solder paste ratio, and peak reflow times and temperatures. Increasing the lead content in the system enables full mixing of the solder joint with a reduced peak reflow temperature, however, previous research is conflicting regarding the effect that lead percentage has on solder joint reliability in this mixed alloy solder joint....

Publisher: Lockheed Martin Corporation

The Perfect Copper Surface

Nov 12, 2015 | Eric Stafstrom; Technic Inc, Garo Chehirian; Tech-Etch.

In order to provide the functionality in today’s electronics, printed circuit boards are approaching the complexity of semiconductors. For flexible circuits with 1 mil lines and spaces, this means no nodules, no pits, and excellent ductility with thinner deposits. One of the areas that has to change to get to this plateau of technology is acid copper plating. Acid copper systems have changed in minor increments since their introduction decades ago. However, the basic cell design using soluble anodes in slabs or baskets has for the most part remained the same. Soluble, phosphorized, copper anodes introduce particulate and limits the ability to control plating distribution....

Publisher: Technic Inc.

Print Performance Studies Comparing Electroform and Laser-Cut Stencils

Nov 05, 2015 | Rachel Miller Short, William E. Coleman Ph.D.; Photo Stencil | Joseph Perault; Parmi.

There has been recent activity and interest in Laser-Cut Electroform blank foils as an alternative to normal Electroform stencils. The present study will investigate and compare the print performance in terms of % paste transfer as well the dispersion in paste transfer volume for a variety of Electroform and Laser-Cut stencils with and without post processing treatments. Side wall quality will also be investigated in detail. A Jabil solder paste qualification test board will be used as the PCB test vehicle....

Publisher: Photo Stencil LLC

Novel Approaches for Minimizing Pad Cratering

Oct 29, 2015 | Chen Xu, Yunhu Lin; Alcatel-Lucent, Yuan Zeng, Pericles A. Kondos; Unovis-Solutions.

With the electronic industry moving towards lead-free assembly, traditional SnPb-compatible laminates need to be replaced with lead-free compatible laminates that can withstand the higher reflow temperature required by lead-free solders. Lead-free compatible laminates with improved heat resistance have been developed to meet this challenge but they are typically more brittle than SnPb laminates causing some to be more susceptible to pad cratering. In this paper, two novel approaches for minimizing pad cratering will be discussed. Preliminary results which validate the two approaches will also be presented....

Publisher: Alcatel-Lucent

Tin Whisker Risk Management by Conformal Coating

Oct 22, 2015 | Linda Woody, William Fox; Lockheed Martin Missiles and Fire Control

The objective of this study is to evaluate conformal coatings for mitigation of tin whisker growth. The conformal coatings chosen for the experiment are acrylic, polyurethane and parylene. Also included in this paper are tin whisker inspection results of tin-plated braiding and wire that was exposed to an environment of 50°C with 50% relative humidity for over five years....

Publisher: Lockheed Martin Corporation

Optimizing the Insulated Metal Substrate Application with Proper Material Selection and Circuit Fabrication

Oct 15, 2015 | Dave Sommervold, Chris Parker, Steve Taylor, Garry Wexler

The ever expanding growth in the use of insulated metal substrates (IMS) in power electronics requires a focus on material and mechanical configuration for each application. By optimizing the material makeup and printed board format, performance and reliability expectations can be further achieved. The thermal performance and electrical isolation needs are driven by the power requirements, but considerations of temperature range, mechanical durability and format, along with the physical package surrounding the substrate must also be managed. With a variety of material configurations and circuit format capabilities, the choices become a balancing of options to maximize performance and minimizing cost through Design For Manufacturability (DFM) in the circuit board fabrication. These challenges present the IMS printed board fabricator with material selections and fabrication processes unlike those for other printed board or ceramic applications....

Publisher: The Bergquist Company

Preparing for Increased Electrostatic Discharge Device Sensitivity

Oct 08, 2015 | Julian A. Montoya, Intel Corporation Hillsboro, Oregon

With the push for ever improving performance on semiconductor component I/O interfaces, semiconductor components are being driven into a realm which makes them more sensitive to electrostatic discharge, potentially increasing in sensitivity by 50% every 3-5 years. Today, the majority of modern day semiconductor components are being designed to meet 250Volts of charge device model sensitivity, and that could decrease to 125Volts in the next 3-5 years, and could again decrease to 50Volts-70Volts in the following 3-5 years. The entire electronics industry must prepare for this challenge....

Publisher: Intel Corporation

Printing of Solder Paste - A Quality Assurance Methodology

Oct 01, 2015 | Lars Bruno and Tord Johnson Ericsson AB and MTEK Consulting AB

Solder paste printing is known to be one of the most difficult processes to quality assure in electronic manufacturing. The challenge increases as the technology development moves toward a mix between large modules and small chip components on large and densely populated printed circuit boards. Having a process for quality assurance of the solder paste print is fast becoming a necessity.

This article describes a method to ensure quality secured data from both solder paste printers and inspection machines in electronic assembly manufacturing. This information should be used as feedback in order to improve the solder paste printing process....

Publisher: Ericsson AB

Gold Stud Bump Flip Chip Bonding on Molded Interconnect Devices

Sep 23, 2015 | Dick Pang, Weifeng Liu, Anwar Mohammed, Elissa Mckay, Teresita Villavert and Murad Kurwa

A molded interconnect device (MID) is an injection molded thermoplastic substrate which incorporates a conductive circuit pattern and integrates both mechanical and electrical functions. (...) Flip chip bonding of bare die on MID can be employed to fully utilize MID’s advantage in device miniaturization. Compared to the traditional soldering process, thermo-compression bonding with gold stud bumps provides a clear advantage in its fine pitch capability. However, challenges also exist. Few studies have been made on thermocompression bonding on MID substrate, accordingly little information is available on process optimization, material compatibility and bonding reliability. Unlike solder reflow, there is no solder involved and no “self-alignment,” therefore the thermo-compression bonding process is significantly more dependent on the capability of the machine for chip assembly alignment....

Publisher: Flex (Flextronics International)

Method for the Manufacture of an Aluminum Substrate PCB and its Advantages

Sep 17, 2015 | Joseph Fjelstad

RoHS legislated restrictions on the materials used in electronics manufacture have imparted significant challenges on the electronics industry since their introduction in 2006. The greatest impacts have been felt by the mandated elimination of lead from electronic solder followed by the demand for the elimination of haloids from flame retardants used in traditional PCB laminates. In the years which have followed the electronics industry has been beset with a host of new challenges in its effort to comply. Failure mechanisms, both new and old, have surfaced which demand solution and the industry suppliers and manufacturing technologists have worked diligently to remedy those vexing faults through the development of a wide range of new materials and equipment for both board manufacture and assembly, along with modifications to the processes used in the manufacture and assembly of printed circuit boards....

Publisher: Verdant Electronics

New High-Performance Organophosphorus Flame Retardant

Sep 10, 2015 | Kimberly M. White, Ph.D., Daniel De Schryver, Ph.D., and Randy Chaya

A new non-halogen flame retardant has been developed and is useful for a variety of high performance applications. This non-reactive phosphorus-based material satisfies fire safety needs for a broad range of resins including epoxy, polyolefin, and polyamide. The combination of excellent flame retardant efficiency, high thermal stability and exceptional electrical properties is unique to this organophosphorus flame retardant and makes it a breakthrough technology for high speed, high frequency use in fast growing wireless and wired infrastructures. Resin performance data, including formulations with synergists, are presented in this paper....

Publisher: Albemarle Corporation

Embedded Fibers Enhance Nano-Scale Interconnections

Sep 03, 2015 | V. Desmaris, S. Shafiee, A. Saleem, A. Johansson and P. Marcoux

While the density of chip-to-chip and chip-to-package component interconnections increases and their size decreases the ease of manufacture and the interconnection reliability are being reduced. This paper will introduce the use of embedded fibers in the interconnections as a means of addressing these issues....

Publisher: Smoltek AB

Adhesive Backed Plastic Stencils vs Mini Metal Stencils

Aug 27, 2015 | Bob Wettermann, MIT

Ever since there has been a widespread usage of surface mount parts, the trend of continued shrinkage of devices with ever finer pitches has continued to challenge PCB assemblers for the rework of same. Todays' pitches are commonly 0.5 to 0.4mm with packages of tiny outline sizes, 5 -10mm square, making the rework of such devices a challenge. In addition to the handling and inspection challenges comes the board density. Spacing to neighboring components continues to be compressed so the rework techniques should not damage neighboring components....

Publisher: BEST Inc.

Challenges for Step Stencils with Design Guidelines for Solder Paste Printing

Aug 25, 2015 | Carmina Läntzsch, Georg Kleemann

The stencil printing process is one of the most critical processes in the electronic production. Due to the requirement: "faster and smaller" it is necessary to place components with different paste volume close together without regard to solder paste printing. In our days it is no longer possible to control the solder paste volume only by adjustment of the aperture dimensions. The requirements of solder paste volumes for specific components are realized by different thicknesses of metal sheets in one stencil with so called step stencils. The step-down stencil is required when it is desirable to print fine-pitch devices using a thinner stencil foil, but print other devices using a thicker stencil foil.

The paper presents the innovative technology of step-up and step-down stencils in a laser cutting and laser welding process. The step-up/step-down stencil is a special development for the adjustment of solder paste quantity, fulfilling the needs of placement and soldering. This includes the laser cutting and laser welding process as well as the resulting stencil characteristics and the potential of the printing process....

Publisher: LaserJob

SELECT CONFORMAL COAT FORMULATION FOR PCB ENVIRONMENT

Aug 20, 2015 | Wes Noble

Temperature and Humidity on Selective Conformal Coating It is well known that selective conformal coating on printed circuit board (PCB) assemblies provides unparallel protection for PCB’s. Nevertheless, concentrated conditions of humidity, water, and high temperatures can have negative effects on the conformal coating itself causing it to fail and become inapt for its intended purpose. Taking this into consideration, it is prudent to choose the right type of conformal coating that best suits the application and environmental conditions under which an assembly is likely to undergo in use. The proper conformal coating will significantly reduce the likelihood of failure/rejection, saving both valuable time and money for any manufacturing process....

Publisher: ETS - Energy Technology Systems, Inc.

Implementing Robust Bead Probe Test Processes into Standard Pb-Free Assembly

Aug 20, 2015 | John McMahon P.Eng, Tom Blaszczyk, Peter Barber

Increasing system integration and component densities continue to significantly reduce the opportunity to access nets using standard test points. Over time the size of test points has been drastically reduced (as small as 0.5 mm in diameter) but current product design parameters have created space and access limitations that remove even the option for these test points. Many high speed signal lines have now been restricted to inner layers only. Where surface traces are still available for access, bead probe technology is an option that reduces test point space requirements as well as their effects on high speed nets and distributes mechanical loading away from BGA footprints enabling test access and reducing the risk of mechanical defects associated with the concentration of ICT spring forces under BGA devices.

Building on Celestica's previous work characterizing contact resistance associated with Pr-free compatible surface finishes and process chemistry; this paper will describe experimentation to define a robust process window for the implementation of bead probe and similar bump technology that is compatible with standard Pb-free assembly processes. Test Vehicle assembly process, test methods and "Design of Experiments" will be described. Bead Probe formation and deformation under use will also be presented along with selected results....

Publisher: Celestica Corporation

NON-CONTACT FLUID DISPENSING WITH PS-8200 JETTING VALVE

Aug 18, 2015 | Brian Stumm

Jetting Valve Technology Superior to Needle Dispensing Compared to traditional needle dispensing technology, jetting valve technology is the most effective method for quick and accurate fluid dispensing. Injection technology has many advantages, it provides a combination of high-speed, high quality and low cost production for fluid dispensing processes. Instead of putting focus on getting the application done, jet dispense technology focuses on performance, providing applications like underfill, potting and encapsulation with more precision than ever before. Improved Fluid Dispensing Speed and Accuracy Non-contact jetting valves offer a significant advantage over traditional needle dispense valves. Jetting Valve Dispenser precision reaches to 200µm with dot diameter or line width as small as 250µm and volumetric dispensing down to .0036µl. Minimum space between lines is 180µm and maximum fluid dispense speed is 200 dots/second. The following video illustrates quick, accurate fluid dispensing for an LED packaging application....

Publisher: ETS - Energy Technology Systems, Inc.

CONFORMAL COATING FOR WATER RESISTANT CIRCUIT ASSEMBLIES

Aug 18, 2015 | Brian Stumm

Why Selectively Conformal Coat the Electronic Assembly? Printed circuit boards (PCBs) are employed in a variety of products and devices, and this means that it might be necessary for your PCBs to be moisture resistant. It is important to choose the right type of conformal coating so you need not worry about the durability of your product. Fortunately, there are several options available that can help, and you can even use selective conformal coating robots to provide proper application of the coating....

Publisher: ETS - Energy Technology Systems, Inc.

ULTRAVIOLET (UV) CURING TECHNOLOGY

Aug 18, 2015 | Wes Noble

What is UV Curing? “Ultraviolet (UV) light is an electromagnetic radiation with a wavelength from 400 nm to 100 nm, shorter than that of visible light but longer than X-rays.” (Source: Wikipedia). Ultraviolet or UV curing is used to create a photochemical reaction using high intensity Ultraviolet (UV) energy or “light” to quickly dry inks, adhesives or conformal coatings. Most materials cure with a UV wavelength around 350 ~ 400nm although some materials require UVC energy near 255nm. There are many advantages to using UV curing over other traditional methods of curing. Not only will it increase production speed, it assists in creating a better bond, and improves scratch and solvent resistance. When compared to other methods of curing, UV curing generates a more reliable cured product at a much higher rate of production in a considerably shorter period of time....

Publisher: ETS - Energy Technology Systems, Inc.

Improve Crimp Quality to Increase Productivity

Aug 17, 2015 | Pete Doyon, VP, Product Management, Schleuniger, Inc.

Since a high percentage of product failures can be traced to poor electrical connections, crimp quality is of paramount importance. There are many factors that come into play that affect crimp quality and knowing the relevant factors, and to what extent each factor affects the end result, will help to guide the process engineer towards achieving the best possible results. ...

Publisher: Schleuniger, Inc.